課程資訊
課程名稱
 電子設計自動化導論
Introduction to Electronic Design Automation 
開課學期
 106-2 
授課對象
 電機資訊學院  電機工程學系  
授課教師
 江蕙如 
課號
 EE3012 
課程識別碼
 901 33700 
班次
  
學分
 3.0 
全/半年
 半年 
必/選修
 選修 
上課時間
 星期一2,3,4(9:10~12:10) 
上課地點
 博理112 
備註
 總人數上限：50人 
Ceiba 課程網頁
 http://ceiba.ntu.edu.tw/1062EE3012_ 
課程簡介影片
 
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課程概述

1. Introduction: History, VLSI design flow, etc.

2. Basics of Computation Theory and Mathematical Optimization

3. High-level synthesis: Design space exploration, resource sharing, etc.

4. Logic synthesis: Technology independent optimization, technology mapping, technology dependent optimization.

5. Timing: timing analysis and optimization, etc.

6. Physical design automation: Partitioning, floorplanning, placement, routing, etc.

7. Design for manufacturability

8. Testing: ATPG, design for test, etc.

9. Advanced topics

 

課程目標
 Electronic Design Automation (EDA) concerns the correctness, reliability, productivity, and optimization of system construction. It is an interdisciplinary field, where electrical engineering and computer science intersect. In EDA, theoretical computer science (including algorithms, complexity, automata, logic, programming languages, etc.) finds rich and practical applications. On the other hand, some of the techniques developed in the EDA community have been much enhanced the state-of-the-art solvers on intractable problems. In this course, we will study some representative problems and solutions making VLSI design an automatic process.
 
課程要求
 Prerequitites:
1) Switching circuits and logic design
2) Computer programming in C or C++ (MUST)
 
預期每週課後學習時數
  
Office Hours
 每週四 13:00~14:00
每週三 13:30~14:00 備註： made by appointments; Wed at BL-629 by Iris, Thu at BL-406 by TA. 
指定閱讀
 Required Text:
Y.-W. Chang, K.-T. Cheng, and L.-T. Wang (Editors). Electronic Design Automation: Synthesis, Verification, and Test. Elsevier, 2009. 
參考書目
 Reference Book:
S. H. Gerez. Algorithms for VLSI Design Automation. John Wiley & Sons, 1999.
 
評量方式
(僅供參考)
  
No.
項目
百分比
說明
1. 
 Homework assignments 
10% 
 two assignments 
2. 
 Mini-projects 
20% 
 two programming assignments 
3. 
 Term project 
20% 
 2- or 3-person teams working on selected problems, presentation and programming are required 
4. 
 Midterm 
25% 
 in-class test 
5. 
 Final 
25% 
 in-class test 
6. 
 Adjustment 
0% 
 The instructor holds the right to adjust the percentage (-5%~+5%) of each item 
 
課程進度
週次
日期
單元主題
第1週
 2/26  Overview 
第2週
 3/05  Introduction 
第3週
 3/12  Computation and optimization 
第4週
 3/19  High-level synthesis 
第5週
 3/26  ILP solver and workstation tutorial 
第6週
 4/02  Spring break 
第7週
 4/09  Logic synthesis: Part I 
第8週
 4/16  Logic synthesis: Part II 
第9週
 4/23  Midterm 
第10週
 4/30  Verification 
第11週
 5/07  Timing analysis 
第12週
 5/14  Physical design: Part I
(slide 40 is added)
 
第13週
 5/21  Physical design: Part II 
第14週
 5/28  Physical design: Part III 
第15週
 6/04  Design for manufacturability 
第16週
 6/11  Project presentation

Some references are provided
 
第17週
 6/18  Dragon Boat Festival & Testing (Appendix) 
第18週
 06/25  Final